The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating vertical transistors.
Current methods of forming vertical transistors typically make use of a selective epi (epitaxial silicon) which is not a common CMOS (complimentary metal-oxide semiconductor.
U.S. Pat. No. 6,069,384 to Hause et al. describes an integrated circuit including vertical transistors with spacer gates having selected gate widths.
U.S. Pat. No. 5,413,948 to Pfiester et al. describes a method for forming a dual transistor structure.
U.S. Pat. No. 5,773,343 to Lee et al. describes a method of fabricating a semiconductor device having a recessed channel structure.
U.S. Pat. No. 5,693,549 to Kim describes a method of fabricating a thin film transistor with supplementary gates.
U.S. Pat. No. 5,670,810 to Tamaki et al. describes a semiconductor device with a vertical field effect transistor (FET).
U.S. Pat. No. 5,429,977 to Lu et al. describes a method for forming a vertical transistor with a stacked capacitor DRAM (dynamic random access memory) cell.
U.S. Pat. No. 5,312,767 to Shimizu et al. describes a method of fabricating a MOS typed field effect transistor.
Accordingly, it is an object of the present invention to provide an improved method of isolating vertical transistors.
Another object of the present invention is to provide an improved method of isolating vertical transistors in combination with the fabrication of those vertical transistors.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical, pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed. Gate oxide is grown over the exposed portions of the wafer and the vertical pillar. Spacer gates are formed over the gate oxide lined side walls of the vertical pillar. Spacer gate implants are formed within the spacer gates, and a second implanted region is formed within the vertical pillar selected from the group consisting of a drain region and a source region that is not the same as the first implanted region to complete formation of the isolated vertical transistor.